Enabling Highly Parallel Test SOCs, Sensors and 3D Packages

Abstract:

Testers are struggling to keep up with Moore’s Law by integrating more channels, power supplies, and analog resources per board.  DFT and adaptive test are driving shorter test times. Memory testers can currently test 256/512 devices in parallel, enabled by highly parallel handling capability. What is the future path of SOC/Sensor test?

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