There are major trends for reduced form factors and increased functionality of ICs as well as enhanced requirements regarding electrical performance and power dissipation. These trends drive TSV packaging and 3D IC solutions. Stacking dies bears a much higher risk for failure than single die technologies: failures may happen in the dies themselves, but additionally in the interposers, in the laminations and in the connections. Bad parts in the stack will corrupt good ones. The worst scenario adds a cost-intensive component such as the a memory on a stack, which is dysfunctional. The KGD concept only partly can solve this. Advanced packaging processes not only require total reliability of the overall supply chain but also require advanced models to reduce the risk of unprofitable output caused by the packaging process itself.