The semiconductor test cell is a complicated environment that creates challenges for the transmission of electrical signals. The resources necessary to power and verify device functionality require large handling and testing equipment.
About Daniela Klostermeier
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Entries by Daniela Klostermeier
While MEMS manufacturing is becoming more and more mature even at 8″ wafer technology, for most suppliers, the integration of various MEMS sensor applications within one package in creating a bottle neck at final MEMS test and calibration.
Abstract: This presentation explains the benefits and risks of high-aspect-ratio though-hole vias in high-density and fine-pitch printed circuit boards used in the test interface. Users are facing challenges as I/O counts increase, circuitry requirements have added to ATE PCB density, and array packages shrink below 0.65 mm pitch.
Determination of the current carrying capacity of contact springs is usually performed by measuring the temperature increase. The upper temperature limit is set by the temperature stability of the spring and the insulation material, the current limit is set accordingly.
The intent of this presentation is to follow-up on the PCB Pad Wear presentation from BiTS 2010. Last year’s presentation focused on the mechanical interaction of various probe tip geometries of socket contacts in 0.8mm pitch, offset PCB pads. This presentation will expand the study to the realm of fine pitch by studying 0.4mm pitch pads, with typical via-in-pad construction.