Enabling Highly Parallel Test SOCs, Sensors and 3D Packages

Abstract:

Testers are struggling to keep up with Moore’s Law by integrating more channels, power supplies, and analog resources per board.  DFT and adaptive test are driving shorter test times. Memory testers can currently test 256/512 devices in parallel, enabled by highly parallel handling capability. What is the future path of SOC/Sensor test?

Test systems can integrate to follow Moore’s Law.  Testers are getting more compact (CTH from Teradyne and Verigy/Advantest). Ten years ago test systems were ~2M$ and device handlers a small percentage of the overall test cell. What is the situation with enabling hardware (handler…) for high parallel test? How do handlers and associated hardware keep pace with device test? How do mechanical structures integrate and follow Moore’s Law?

The “new future” needs to deal with highly integrated devices: Multiple functionalities within one sensor, multiple dies within one package. How can the hardware keep pace with MEMS Fusion and 3D integration?

This paper will provide a mechanical handling solution for testing non-memory devices with high parallelism (144 – 300 devices in parallel).  Also it will provide a solution for testing highly parallel sensors. Sensors have become ubiquitous in consumer (Smartphone, GPS, gaming…), automotive (TPMS – Tire pressure measurement systems, airbags, stability control…), and Industrial applications.  These devices (accelerometers, gyro, pressure, magnet/compass, microphone…) also currently require various stimuli to test.

Version: July 2012
Presented by: Bernhard Lorenz
Presented at: Test Vision 2020