There are many differences between wafer probe and wafer-level test, some obvious, some subtle. There are both electrical and mechanical differences.
Electrical performance requirements dictate the use of spring probes for wafer-level test.
Wafer-level test is final test, so the contact must be low-resistance for accurate DC measurements, high-bandwidth for at-speed functional tests or AC measurements, low-inductance for power delivery, and high-mechanical performance is another important consideration. Packaging, including wafer-level packaging, adds significant variation (tolerance) to the target height. Wafer-level test contacts must have more compliance to accommodate height tolerance than traditional wafer probe technologies, such as vertical probe. Compliance is similar to overdrive – it specifies the recommended probe travel. The greater the compliance, the smaller the effect of underdriving the probe. Among their other advantages, Multitest spring probes have more compliance than traditional Pogo-style probes due to their external-spring design.
Board planarity is also important. Spring probes make solderless contact to the board. Spring probes are preloaded on the board side to prevent chatter. Any deviation from planar consumes some of the spring probe compliance. As wafer-level contactors grow larger, planarity becomes more important. Larger devices are being tested at the wafer level, and multiple sites leverage economic advantage of wafer-level packaging and test.
Examples of balancing stack ups will be shared, illustrating the consideration that must be given to the resin systems, coefficient of thermal expansion & weave direction when using mixed laminates, as well as the addition of inner layer copper pour (thieving) to more evenly distribute copper throughout the layer stack.
There is also a planarity benefit to manufacturing with monolithic books. High-aspect-ratio vias provide a benefit by minimizing the use of sequential lamination which can induce unwanted stress & board warp. An example of how a WLCSP test board using sequential lamination can be improved with the use high aspect ratio vias will be shared.
Multitest’s UltraFlat process improves planarity through a series of post-lamination planarizations. This process provides permanent improvement compared to traditional flat-baking, which is a temporary improvement.
As planarity tolerances reduce to meet the needs of future wafer level testing, there have also been changes in PCB planarity validation techniques, which confirm the planarity where it matters, and not elsewhere. A proposal of a measuring method will be shared.
Version: March 2013
Presented by: Jim Brandes
Presented at: BiTS