Posts

3D Test Challenges and Solutions

Abstract:

The presentations describes different approaches for 3D assembly and test. Existing challenges are analyzed and possible solutions are discussed. The concept of partial stack test and “Known-Good-Stack” is introduced and respective equipment requirements are summarized.

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Quality in 3D Assembly – Is KGD Good Enough?

Abstract:

Issue: There are numerous papers and articles about 3D packages; however, they have not been able to conquer the volume production status. One common issue is how to ensure quality across the overall and more complex supply chain.

For assembly this means that stacking dies bears a much higher risk for failure than single die technologies. Bad parts in the stack will corrupt good ones. The worst scenario adds a cost-intensive component such as a memory on a stack, which is dysfunctional. The KGD concept can only partly solve this.

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3D ICs – Smart, New Test Insertions make the difference

Abstract:

The additional risks in 3D packaging basically result from two facts:

1 . Stacking multiple dies into a 3D package also multiplies the probability of having a defective package in the end. In final test a package yield of 90 percent is realistic for standard packages. For a four-dies stacked package having 90 percent yield per die will bring down the overall yield to only 60 percent.

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Test Strategies for 3D ICs – Is KGD Good Enough? Is there a KGD?

Abstract:

3D packages have not been able to conquer the volume production. One common issue is how to ensure quality across the overall and more complex supply chain. Standardization efforts like Wide I/O memory and HMC (Hybid Memory Cube) Consortium work on defining industry-wide interfaces and standard requirements.

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3D Technology Fusion – Is KGD Good Enough? Why New Test Strategies are Needed? Abstract:

Abstract:

Issue:

There are major trends for reduced form factors and increased functionality of ICs as well as enhanced requirements regarding electrical performance and power dissipation. These trends drive TSV packaging and 3D IC solutions. Stacking dies bears a much higher risk for failure than single die technologies: failures may happen in the dies themselves, but additionally in the interposers, in the laminations and in the connections. Bad parts in the stack will corrupt good ones. The worst scenario adds a cost-intensive component such as the a memory on a stack, which is dysfunctional. The KGD concept only partly can solve this. Advanced packaging processes not only require total reliability of the overall supply chain but also require advanced models to reduce the risk of unprofitable output caused by the packaging process itself.

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Test and Test Equipment

Version: January 2012
Presented by: Rother Barth

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