A recognized standard for evaluating the CCC (current carrying capacity) of an interconnect used at wafer probe has been the ISMI Probe Council Current Carrying Capability Measurement Guideline, published by International SEMATECH Manufacturing Initiative in 2009. The ISMI test is a relatively simple way to observe the interconnect force degradation as a function of current applied. The guideline evaluates at what point the contact sees a 20% force reduction. This 20% force reduction, means that the contact has been permanently deformed, and this is therefore a truly destructive test.
High Bandwidth Memory (HBM) is a new type of memory device bringing higher bandwidth, smaller form factor and lower power consumption to keep up with processor performance growth. This is achieved by stacking multiple DRAM dies onto a base controller die, which are interconnected by through-silicon vias (TSV) and micro bumps. The advanced wafer level packaging to fabricate HBM chips also introduce increasing challenges in testing and handling of these delicate devices.
Today cmWave (3-30GHz) and mmWave (30-300GHz) applications have become mainstream. Packaging has become obsolete and wafers are becoming the new final test package. Testing automotive radar on wafer at 80 GHz and 150 degC was previously a fantasy, but is now a reality. With high power simulation tools and 110 GHz VNA’s it’s possible to design and fabricate hardware for these extremely high frequency, high temperature applications.
Test probe selection decisions must be supported with verifiable and repeatable performance data. This include the lab data describing the statistically predicted field performance of the test probe. Presented will be lab data describing the performance of several mainstream probe architectures for contacting Wafer Level Chip Scale Packages (WLCSP). The goal of this paper is to create a common understanding of how to read, interpret, and communicate data for selecting the right probe technology for WLCSP test applications.
This paper works to create a level playing field for interpreting, communication, and apply the electrical and mechanical specifications that describe test probe performance. Presented will be lab data describing the performance of Wafer Level Chip Scale Package (WLCSP) contacting technology.
Spring probes are becoming a viable alternative to traditional probe card technologies in testing WLCSP devices.
Manufacturing spring probes at this scale is very challenging, and various suppliers have taken different approaches to building them. This presentation will explore the various probe architectures that are commercially available, and present detailed mechanical and electrical lab performance of each style. Each contact technology will be presented from a mechanical and electrical reliability standpoint, as well as cost and complexity.
Wafer Level Chip Scale Package (WLCSP) devices are used because they offer very low cost, small footprint packages to be directly mounted into smartphones, tablets, other mobile devices and automotive applications. The type of technologies targeted for fan-in WLCSP packaging includes PMICs, transceivers, microcontrollers, IoT applications, MEMS and more.
Spring probes have now been widely adopted as an alternative to well-known probe card technologies in testing WLCSP packaging. Several studies have been presented on this topic at BiTS and other conferences, and will be summarized.
Xcerra is continuously improving the spring probes it manufactures for Wafer-Level test. This presentation describes an improvement that extends the life of a WLCSP probe that is used in a harsh environment.
In 2015 Xcerra introduced spring probe technology capable of contacting WLCSP devices down to 0.3 mm pitch. Probeheads employing this technology shipped to multiple sites. The technology performs well, providing excellent yields and long life.
The wafer level chip scale package (WLCSP) has emerged as one of the best device packaging solutions for the continuing trend towards smaller, thinner, lighter, and less power end products. Compared with face up wire bonding flip chip, WLCSPs provide the shortest possible leads, the lowest inductance, the highest frequencies, the best noise control, the highest density, and the greatest number of I/Os in the smallest device footprints with the lowest profile.